Early exception detection

ABSTRACT

A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.

BACKGROUND

[0001] This invention relates to exception handing in a programmableprocessor.

[0002] One challenge in designing a programmable microprocessor, such asa digital signal processor, is the handling of exceptions. An exceptionmay be a software-initiated event that arises when an error isencountered, such as invalid instruction or bus error. In designing aprocessor, it is desirable to handle events as quickly as possible.However, this typically involves additional hardware that may increasethe power consumption of the processor.

[0003] Exceptions are generally detected when an instruction is beingexecuted. These detected exceptions are then generally reported forprocessing after the processor has executed the instruction. If anexception condition can be detected before the instruction is executed,however, the processing of an exception may be handled more quickly.

DESCRIPTION OF DRAWINGS

[0004]FIG. 1 is a block diagram illustrating an example of aprogrammable processor according to an embodiment of the invention.

[0005]FIG. 2 is a block diagram illustrating a prefetch unit and analignment unit according to an embodiment of the invention.

[0006]FIG. 3 is a flow diagram illustrating a mode of operationaccording to an embodiment of the invention.

[0007]FIG. 4 is a block diagram of exemplary prefetch buffers loadedwith respective data blocks and exception status information inaccordance with an embodiment of the invention.

DESCRIPTION

[0008]FIG. 1 is a block diagram illustrating an example of aprogrammable processor according to an embodiment of the invention. Aprocessor 2 may include an execution unit 4 and a control unit 5. Thecontrol unit 5 may send control signals 6 to control the flow ofinstructions and/or data through the execution unit 4. For example,during the processing of an instruction, the control unit 5 may directthe various components of the execution unit 4 to decode the instructionand correctly perform the corresponding operation including, forexample, writing the results back to memory. The execution unit 4 mayinclude one or more pipelines that may facilitate execution of multipleinstructions in rapid sequence.

[0009] The control unit 5 may include a prefetch unit 7 coupled to amemory device. Alternatively, the prefetch unit 7 may be integrated intothe memory device. As described in detail below, the prefetch unit 7 maystore one or more instructions and exception status informationassociated with the data block and instructions. The control unit 5 mayfetch a data block from memory that contains one or more instructions.Moreover, the control unit 5 may detect whether an exception conditionassociated with the data block or an instruction in the data blockexists. The control unit 5 may generate exception status information,and the exception status information may be stored in the prefetch unit7 with the data block. Subsequently, an instruction may be issued inparallel with at least part of the exception status informationassociated with that instruction.

[0010] The control unit 5 may also include an instruction alignment unit8 for aligning an instruction before it is issued. The instructionalignment unit 8 may be adapted to handle variable width instructions.The instruction alignment unit 8 may ensure that instructions areproperly aligned when they are sent to the execution unit 4 forprocessing. Moreover, the instruction alignment unit 8 may also ensurethat at least part of the exception status information associated withan instruction is sent to (i.e., issued to) the exception managementlogic 9 in parallel with the issuance of the instruction.

[0011] When an instruction is issued by the control unit 5, it may beexecuted in the execution unit 4. For instance, the execution unit 4 maydecode the instruction and perform specified operations such as, forexample, adding or multiplying two numbers. The execution unit 4 maycontain specialized hardware for performing the operations including,for example, one or more arithmetic logic units (ALU's), floating-pointunits (FPU) and barrel shifters, although the scope of the presentinvention is not limited in this respect.

[0012] When an instruction is issued to the execution unit 4, at leastpart of the exception status information associated with the instructionmay be sent to the exception handling logic 9. The exception handlinglogic 9, for instance may process and/or propagate the exception statusinformation in parallel with the execution of the instruction in theexecution unit 4.

[0013] The memory may be either internal or external to the processor 2.For instance, if memory is internal to the processor 2, the prefetchunit 7 may be integrated into the memory. The control unit 5 may beadapted to detect one or more exception conditions. If an exceptioncondition is detected, exception status information may be stored in theprefetch unit 7 to reflect this fact. Moreover, exception statusinformation may include information identifying the exception conditionthat was detected. If an exception condition is not detected, theexception status information may reflect this fact. After being storedin prefetch unit 7, an instruction and at least part of its associatedexception condition may then be issued in parallel to the execution unit4 and the exception handling logic 9.

[0014] There are several exception conditions that the control unit 5may detect when an instruction is prefetched from memory. For instance,when a data block is prefetched, the control unit 5 may detectexceptions such as a memory error or a bus error. The control unit 5 maydetect if an instruction is improperly aligned in memory, or if all orpart of the data block resides in a memory location (e.g. a memory pageor a cache line) that is not currently accessible.

[0015] The control unit 5 may include comparative logic to compare thedata block or the data block's address, for example, to bad instructionsor bad memory addresses. In addition, the control unit 5 may includelogic to conduct a parity check on the data block to determine whetherthe data block may have become corrupted after it was sent from memory.However, the scope of the invention is not limited by the type ofexception, and specific exceptions listed herein are included asexamples.

[0016]FIG. 2 is a block diagram in accordance with an embodiment of theinvention. FIG. 2 illustrates a prefetch unit 7 coupled to aninstruction alignment unit 8. The prefetch unit 7 may include a numberof prefetch buffers 16, 17 for storing prefetched data and exceptionstatus information associated with one or more instructions in theprefetched data. Although FIG. 2 shows two prefetch buffers 16, 17, anynumber of prefetch buffers could be implemented in accordance withembodiments of the invention.

[0017] The prefetch buffers 16, 17 may be instruction registers havingany particular width. By way of example, embodiments of the inventionare described below where the prefetch buffers are instruction registerswith a width sufficient to hold 64 instruction bits and the exceptionstatus information. Moreover, in the embodiments described below, alargest instruction in an instruction set supported by the processor 2is a 64 bit instruction. The invention, of course, may be implementedwith prefetch buffers of any particular size, and instruction setssupporting any number of different width instructions.

[0018] By way of example, an instruction set supported by the processor2 may include instructions of varying widths. For instance, instructionsmay be 16 bit instructions, 32 bit instructions, or 64 bit instructions.The control unit 5 may cause data blocks to be loaded into the 64 bitprefetch buffers. An instruction may therefore reside in one of theprefetch buffers 16, 17, or alternatively an instruction may be spreadacross the prefetch buffers 16, 17. The control unit 5 may also generateexception status information, for instance, describing the exceptionstatus of the instructions contained in a given data block. Thus, if aninstruction is spread across the prefetch buffer 16, 17 it may haveexception status information associated with both data blocks thatcontain part of the instruction.

[0019] Because more than one instruction may be contained in a given theprefetch buffer 16, 17, or a given instruction may be spread across theprefetch buffers 16, 17, the instruction alignment unit 8 may ensurethat an instruction is properly aligned when the control unit 5 issuesthe instruction to execution unit 4. The instruction alignment unit 8may include one or more alignment multiplexers 20 to ensure properinstruction alignment. When an instruction is issued to execution unit4, at least part of the exception status information associated with theinstruction may be sent to the exception management logic 9.

[0020] The exception status information may be stored in prefetchbuffers 16, 17 as an exception word. For instance, each bit in theexception word may correspond to a particular exception that may bedetected by control unit before the instruction is issued. In oneembodiment, issuing at least part of the exception status informationcomprises sending an n-bit exception word through an n-input OR gate 22to the exception management logic 9. Thus, the event management logic 9may receive a signal that only indicates whether an exception wasdetected prior to issuance of the instruction.

[0021] The exception status information may describe whether anexception condition is associated with a given data block. Thus anyinstruction contained in the same data block may have the sameassociated exception status information. If an instruction is spreadacross more than one data block, its exception status information mayinclude information describing the exception status of one or both ofthe data blocks. For instance, in an instruction is spread across twodata blocks, the respective bits of the data blocks may be passedthrough a logic gate to create exception status information describingthe whole instruction.

[0022] As mentioned above, the exception status information may be savedas an exception word in the prefetch unit 7. For example, the exceptionword may contain any number of bits. Moreover, the width of theexception word may depend on the number of different exceptions that thecontrol unit 5 is adapted to detect before the instruction is sent tothe execution unit 4. Generally, the width of the exception word shouldbe at least the number of bits required to encode all the exceptions,although it could be even larger.

[0023]FIG. 3 is a logic flow diagram according to an embodiment of theinvention. As shown, a block of data is fetched (32). For example, thecontrol unit 5 may fetch the data from a memory source either internalor external to processor 2. Exception status information is thengenerated (34). The exception status information may indicate whether ornot particular exceptions were detected.

[0024] For example, the control unit 5 may generate the exception statusinformation by implementing comparative logic that compares the addressof the data block to invalid addresses, improper address, misalignedaddresses or the like. Some addresses, for instance, may be accessibleonly when the processor 2 is in a particular mode. Thus, the comparativelogic may simply compare the address of the data block to the addressesthat are accessible given the current mode of the processor 2. Also, asmentioned above, the control unit 5 may conduct a parity check todetermine whether data is corrupted. The exception status informationmay reflect the results of these or other queries made by the controlunit 5.

[0025] After fetching the data block (32) and generating exceptionstatus information (34), the exception status information may be storedwith the data block (36). The prefetch unit 7 may be used to store theexception status information with the data block. Then, an instructionmay be detected from the data block (38) and the instruction and atleast part of the exception status information may be issued in parallel(40, 42).

[0026] The instruction alignment unit 8 may be used to detect aninstruction from the data block (38). By detecting the width of theinstruction. As described above, a single data block may contain one ormore instructions, or only part of two different instructions. Theinstruction alignment unit 8 may be adapted to detect instructions fromthe data block so that the instructions may be issued to the executionunit 4.

[0027] If only part of the instruction is in the data block, the rest ofthe instruction may be contained in the next data block to be fetched.Thus, fetching another data block containing the rest of the instructionmay occur before the instruction is issued. The prefetch unit 7 maycontain a number of buffers 16, 17 so that multiple data blocks may befetched before an instruction in one or more of those data blocks isissued.

[0028] After the instruction has been detected (38), the instruction maybe issued in parallel with the issuance of at least part of theexception status information (40, 42). Issuing the instruction (40) maycomprise sending the instruction to a decoder in the execution unit 4.Moreover, issuing at least part of the exception status information (42)may comprise sending the bits of an exception word through an OR gate tothe exception handling logic 9.

[0029]FIG. 4 is a block diagram of exemplary prefetch buffers 16, 17,loaded with respective data blocks and exception status information. Thedata blocks loaded into prefetch buffers 16, 17 may include instructionsor parts of instructions. The exception status information may compriseone or more exception words. The exception words, for instance may beloaded into prefetch buffers 16, 17 before or after the respective datablocks. The exception words may indicate whether the control unit 5detected one or more exception conditions associated with the data blockor a particular instruction in the data block.

[0030] For example, in one embodiment the exception word may includeexception identification bits identifying different exceptions. Thenumber of exception identification bits may depend on the number ofexceptions that the control unit 5 is adapted to detect. For example, ifcontrol unit 5 is adapted to detect only two exceptions, exception wordmay have at least two exception identification bits. If the control unit5 is adapted to detect three exceptions, the exception word may have atleast three exception identification bits. If the control unit 5 isadapted to detect five different exceptions, the exception word may haveat least five exception identification bits.

[0031] By way of example, one particular implementation supports afive-bit exception word. The respective five bits correspond to one offive exception conditions that the control unit 5 is adapted to detectprior to the issuance of the instruction. One of the five bits maycorrespond to an exception condition relating to multiple cacheprotection buffer hits. Another of the five bits may correspond to anexception condition relating to an address that is misaligned. Stillanother of the five bits may correspond to an exception conditionrelating to protection violation. Yet another of the five bits maycorrespond to an exception condition relating to a cache protectionbuffer miss. Still yet another of the five bits may correspond toexception condition relating to memory access violations. These or otherexception conditions may be accounted for in the exception word.

[0032] Various embodiments of the invention have been described. Forexample, methods and apparatus for early detection of exceptions havebeen described. These methods and/or apparatus may be implemented in aprocessor to improve the processor's performance. The processor may beimplemented in a variety of systems including general purpose computingsystems, digital processing systems, laptop computers, personal digitalassistants (PDA's) and cellular phones. In such systems, the processormay be coupled to a memory device, such as a FLASH memory device or astatic random access memory (SRAM) that stores an operating system andother software applications. These and other embodiments are within thescope of the following claims.

What is claimed is:
 1. A method comprising: issuing the instruction andat least part of the exception status information in parallel.
 2. Themethod of claim 1, further comprising: detecting the width of theinstruction prior to issuing the instruction and at least part of theexception status information in parallel.
 3. The method of claim 1,wherein issuing the instruction and at least part of exception statusinformation in parallel comprises: sending the instruction to a decoder;and sending the exception status information through an OR gate toexception handling logic.
 4. The method of claim 1, further comprising:fetching at least one data block; generating exception statusinformation about the data block; storing the exception statusinformation with the data block; and detecting at least part of aninstruction within the data block.
 5. The method of claim 4, whereingenerating exception status information includes generating informationidentifying that a particular exception condition was detected.
 6. Themethod of claim 4, wherein generating exception status informationcomprises generating information indicating that a particular exceptioncondition was not detected.
 7. The method of claim 4, furthercomprising: if only part of the instruction is in the data block,fetching another data block containing the rest of the instruction priorto issuing the instruction.
 8. The method of claim 4, wherein storingthe exception status information with the data block comprises storingthe exception status information and the data block in a prefetch unit.9. The method of claim 4, wherein storing the exception statusinformation comprises storing an exception word.
 10. An apparatuscomprising: a control unit including: a prefetch unit comprising atleast one prefetch buffer, wherein, the control unit is adapted to issuethe instruction and at least part of the exception status information inparallel.
 11. The apparatus of claim 10, wherein the control unit isfurther adapted to: fetch at least one data block; generate exceptionstatus information about the data block; store the exception statusinformation and the data block in the prefetch unit; and detect at leastpart of an instruction within the data block.
 12. The apparatus of claim10, wherein the prefetch unit includes at least two prefetch buffers,and the control unit is further adapted to: fetch another data block;generate exception status information about the another data block; andstore the exception status information and the another data block in theprefetch unit.
 13. The apparatus of claim 10, the control unit furthercomprising an instruction alignment unit coupled to the prefetch unit,the instruction alignment unit adapted to align the instruction beforethe instruction is issued.
 14. The apparatus of claim 10, furthercomprising a decoder coupled to the control unit, the control unitfurther including exception handling logic, wherein issuing theinstruction and at least part of the exception status information inparallel comprises: sending the instruction to the decoder; and sendingthe exception status information through an OR gate to the exceptionhandling logic.
 15. The apparatus of claim 10, further comprising memorycoupled to the control unit, wherein fetching at least one data blockcomprises fetching at least one data block from memory.
 16. Theapparatus of claim 10, the control unit further including a memorydevice, and wherein the prefetch unit resides in the memory device. 17.A system comprising: a static random access memory device; and aprocessor coupled to the memory device, wherein the processor includesan execution unit and a control unit, the control unit including aprefetch unit and exception handling logic, the control unit adapted to:fetch at least one data block; generate exception status informationabout the data block; store the exception status information and thedata block in the prefetch unit; detect at least part of an instructionwithin the data block; in parallel, issue the instruction to theexecution unit and issue at least part of the exception statusinformation to the exception handling logic.
 18. The system of claim 17,wherein the control unit is further adapted to: fetch another datablock; generate additional exception status information about theanother data block; and store the additional exception statusinformation and the another data block in the prefetch unit.
 19. Thesystem of claim 17, wherein the prefetch unit includes at least twoprefetch buffers.
 20. The system of claim 17, wherein issuing theinstruction and at least part of exception status information inparallel comprises: sending the instruction to the decoder; and sendingthe exception status information through an OR gate to the exceptionhandling logic.